First smartphone to run HarmonyOS 7 and include chip design breakthrough LogicFolding

SHENZHEN, CHINA – Media OutReach Newswire – 28 September 2026 – Huawei released the HUAWEI Mate XT 2 | ULTIMATE DESIGN trifold smartphone on September 7. The phone is the first to run HarmonyOS 7, and is the slimmest and largest foldable smartphone in the industry. The Mate XT 2's Kirin 9050 chip also includes a major breakthrough in semiconductor design. As the first smartphone to feature the LogicFolding Tau (τ) Chip, the Mate XT 2 marks the chip's official entry into mass commercialization. World-class engineering and design The device is proving popular with consumers due to its foldable wing-like form, which means it can be opened up, transforming the phone into a tablet. The engineering to make this possible is unprecedented. The glass screen must be tough enough to withstand daily use, whilst being able to fold thousands of times. The hinge to allow the screen to fold is the first of its kind. Once open, the handset is just 3.5mm thick. However, the screen is not the only remarkable folding technology in the device. The first chip with semiconductor design breakthrough, LogicFolding The Mate XT 2 Ultimate Design includes a major breakthrough in semiconductor design. The phone is the first to use Huawei's LogicFolding Tau chip Kirin 9050 Pro. Designed by engineers in Huawei's HiSilicon team, the chip offers a solution to the problem of geometric scaling. With Moore's law (the historical observation that the number of transistors on a microchip doubles approximately every two years) believed to be reaching its physical limit, making chips smaller is becoming more challenging and costly. For Huawei, faced with external restrictions, the need to find a solution came sooner than expected. In May this year, He Tingbo, President of Huawei's HiSilicon division, unveiled a new way of designing and making chips, alongside a new law to measure their performance, the τ (Tau) Scaling Law. The work led to Ms He being recently named one of the world's leading AI innovators by Time Magazine. The point of shrinking transistors was never the smallness itself, it's what the smallness delivered. Shoppers looking to buy the latest smartphone don't care if the chips inside have 7, 5 or even 2-nanometer nodes, they care about the performance of the device in their hands. What matters to consumers is the time it takes for a task to be completed, a video to be shared or a game to load. The performance of the chip should be measured in the same way: by time, not size. This is why Huawei proposed τ (Tau) Scaling Law as an alternative to Moore's Law. Breaking through barriers to improve performance The Kirin 9050 Pro uses 3D integration to boost performance. Traditional chip advancement focussed on packing more and more transistors into a linear plain by making each one smaller. LogicFolding uses 3D integration to reduce the distance between transistors by stacking them on top of one another, increasing the number of transistors whilst reducing the distance between them. In fact, in the Kirin 9050 Pro transistor density has risen from approximately 155 to 238 million transistors per square millimetre. That's an equivalent increase to what was achieved in the previous three years using geometric shrinking. It was thought that stacking active transistors on top of each other and sealing them inside a solid mobile device would present an engineering challenge. Power turns into heat, which in a confined space would raise the temperature and ultimately break the device. The key to the solution came in recognising that integrated chips have both transistors and circuits. As He Tingbo explains in her IEEE article, Huawei's τ Chip Was Supposed to Melt?, the inner workings of a chip can be compared to an office worker's day of work. Many office workers will use more energy on their commute to and from the office than they do at their desk because they are moving around more on the road. The 'work' part of their day is not the most energy intensive part as they are often seated at their desk. The same is true for chips. The most energy intensive part of the process is the 'commute', moving data from point A to point B, not processing it. Integrated circuits use power in two main ways. The first is switching, flipping a transistor gate to change a bit from 0 to 1 and back. The second is the transmission of that data, moving the bits from one part of the chip to another. This is important in mobile phones where a lot of performance requirements are asked of a single chip. Equally, however, in a large AI cluster 80% of the energy is used in the moving the data, not processing it. In both cases, LogicFolding reduces the space between transistors which in turn reduces the power used. The previous assumption that packing transistors on top of one another would increase the heat turned out to be false. In fact,...